1. Technical Field
The present invention relates in general to buffer management for improved PCI-X or PCI bridge performance and in particular to a system and method for managing transactions across a PCI-X or PCI bridge. Still more particularly, the present invention relates to waiting for, increasing, and/or optimizing the available buffers for transaction size or sizes across a PCI-X or PCI bridge. Herein, the terms PCI-X or PCI bridge refer to a PCI-X to PCI-X or PCI to PCI bridge which connects two PCI buses. PCI-X is a high performance extension of the PCI bus which is currently being developed.
2. Description of the Related Art
Peripheral component interconnect (PCI) specifications have been developed and continued to be improved for communicating between a host computer, systems memory and various devices or adapters, such as devices on the bus, plug-in cards, or integrated adapters. The specifications for PCI have been detailed in PCI specification version 2.2 published in December 1998. PCI-X is a draft specification being developed by the PCI Special Interest Group (PCISIG) as an addendum to the PCI specification targeted to be released mid 1999. PCI-X is intended to be backward compatible. Therefore, both bridge interfaces must be capable of operating in either PCI or PCI-X mode (PCI to PCI, PCI-X to PCI-X, PCI to PCI-X, PCI-X to PCI). These specifications are incorporated by reference herein.
Various transactions, such as input/output (I/O) transactions and Direct Memory Access (DMA) transactions, occur across the PCI-X or PCI bridge between the host computer and the various devices and between I/O devices and system memory. Delayed transactions across such bridges require the master to repeat the transaction until it ceases to receive a retry and the transaction completes. However, the problem with delayed transactions is that the master has to continue to repeat and wait until appropriate buffers are available or it receives the data requested which results in the tie up or back up of transactions across the host bridge. Split transactions across such bridges avoids having the master wait and repeat transactions and allows commands to be accepted by a bridge and the results (data) returned later with the bridge acting as the master. However, split transactions may result in the decomposition of large transactions into smaller transactions. Smaller transactions processed across the bridge are typically less efficient in using the bus than large transactions.
For example, the current draft PCI-X specification provides programming capabilities of the size of split read requests (up to 4 k bytes). The PCI-X draft specification further provides the maximum number of outstanding requests that a device or adapter may be able to issue (up to 32 requests) and also requires that the device or adapter accept an outstanding read completion in one bus transaction without retry. A bus transaction may include an address phase, an attribute phase, a target response phase, one or more data phases, and a turn-around phase. A PCIX-to-PCIX (PtP) bridge is currently allowed to accept a read completion transaction or posted memory write transaction when one (1) ADB (an ADB is a block of data having 128 bytes that is aligned on a 128 byte address boundary) is available in the bridge buffer space. This availability of one (1) ADB of buffer space could result in larger read completions being broken down into smaller read completions when the PtP bridge accepted part of the read completion data and then disconnected. The problem exists in that when one (1) ADB transactions are buffered in the bridge, they will be forwarded to the other side of the bridge and executed as single ADB transfers. These single ADB transfers reduce the effective bandwidth of the bus where the data is being received and the bus where it is being forwarded.
The problem becomes especially worse when the system is busy. The problem starts when the system is busy, and the problem perpetuates itself until the system becomes less busy. An example of such a problem is explained by referring to FIG. 2. The PtP bridge 22 have buffers to receive and store data from bus 20 until the bridge 22 is able to obtain access to the other bus 24 and forward the data to the final destination. FIG. 2 shows the types of buffering needed in a PtP bridge 22, which are Posted Memory Write (PMW) buffer 30, Split Read Completion (SRC) and Split Write Completion (SWC) buffer 32, and Split Read Request (SRR) and Split Write Request (SWR) buffer 34. The transaction types for the PtP bridge 22 are Posted Memory Write (PMW), Split Read Completion (SRC), Split Write Completion (SWC), Split Read Request (SRR), and Split Write Request (SWR). A split completion may be a SRC or a SWC, and a split request may be a SRR or a SWR. The buffers shown in FIG. 2 are shown only for transactions from PCI-X bus 20 (bus #1) to PCI-X bus 24 (bus #2). Similar buffers exist for the transactions from PCI-X bus 24 (bus #2) to PCI-X bus 20 (bus #1) but are not shown in FIG. 2 since the single set of buffers is sufficient to describe the problem.
The problem may occur in either the PMW buffer 30 or the SRC buffer 32. The key problem is a result from managing the buffers in single ADB sizes as opposed to fixed buffers of fixed sizes. For example, the SRC buffer 32 is configured to hold 2 k bytes of data (16 ADBs), and the SRC buffer 32 is full of data that consists of 4 separate transactions of 4 ADBs each. The full SRC buffer 32 may be the result of bus #1 (bus 20) being faster than bus #2 (bus 24) or bus #2 becoming very busy with several read requests. The PtP bridge 22 is granted access to bus #2, and the PtP bridge 22 starts to forward one of the SRC from the SRC buffer 32. When one (1) ADB of data has been forwarded to bus #2, the PtP bridge 22 starts to accept a SRC from bus #1. Since bus #1 is faster than bus #2, the available ADB in the SRC buffer 32 is filled before the bridge 22 is able to empty a second ADB to bus #2. Thus, the bridge 22 needs to disconnect the bus #1 transaction at the first ADB boundary. As the sequence continues wherein the bridge 22 forwards each ADB""s worth of data to bus #2, an ADB in the SRC buffer 32 is freed up which is filled by SRC transactions that are only one (1) ADB in size followed by a disconnect. The SRC buffer 32 in the bridge 22 is then filled with SRC transactions that are one (1) ADB in size, which do not efficiently use the bus which receive these forwarded transactions.
It would therefore be advantageous and desirable to provide buffer management for improved PCI-X or PCI bridge performance. It would be advantageous and desirable to provide a system and method for managing transactions across a PCI-X or PCI bridge. It would also be advantageous and desirable to provide a system and method that waits for, increases, and/or optimizes the available buffer space for transaction size or sizes across a PCI-X or PCI bridge and that times the optimal processing of respective transactions depending on transaction size and available buffer space.
It is therefore one object of the present invention to provide buffer management for improved PCI-X or PCI bridge performance.
It is another object of the present invention to provide a system and method for managing transactions across a PCI-X or PCI bridge.
It is a further object of the present invention to provide a system and method of waiting for, increasing, and/or optimizing of available buffer space for transaction size or sizes across PCI-X or PCI bridges and of timing for optimally processing respective transactions depending on the transaction sizes and the available buffer space.
The foregoing objects are achieved as is now described. Buffer management for improved PCI-X or PCI bridge performance. A system and method for managing transactions across a PCI-X or PCI bridge, and a system and method of waiting for, increasing, and/or optimizing the available buffers for transaction size or sizes across a PCI-X or PCI bridge. Transactions are processed across the bridge, and the bridge has buffers with actual available buffer space used for receiving and processing the transactions. Transaction size of the transaction is determined. The system and method sets an available free block which is a set amount of available buffer space that is to be freed up before certain larger size transactions (multiples of ADBs) are processed. The system and method waits for the actual available buffer space to free up and reach the available free block. Certain larger transactions are processed when the actual available buffer space has reached the available free block. The processing of the transaction involves accepting the transaction if the transaction size is not greater than the actual available buffer space, retrying the transaction for processing by the bridge when the transaction size is less than the available free block but greater than the actual available buffer space, retrying the transaction when the transaction size is greater than both the available free buffers and the available free block until the available buffers is greater than or equal to the available free block, and then accepting the transaction and then disconnecting once the actual available buffers are filled or at the end of the transfer.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.